STARAN® has a number of array modules, each with a multidimensional access (MDA) memory. The implementation of this memory with random-access memory (RAM) chips is described. Because data can be accessed in either the word direction or the bit-slice direction, associative processing is possible without the need for costly, custom-made logic-in-memory chips.

SIMD machine architects must choose an interconnection network to provide interprocessor communication. The universality of a network is its ability to simulate arbitrary interconnections of the processing elements. We examine the universality of five particular networks which cover the types used in the llliac IV, STARAN, Omen, SlMDA, and RAP machines. They also cover the types discussed by Feng, Lang, Lawrie, Orcutt, Siegel, and Stone. We give O((log2N)2 ) algorithms, where N is the number of processing elements, for the Perfect Shuffle, PM21, WPM21, and Cube networks to simulate arbitrary interconnections (Orcutt has given an O(Nl/2log2N) algorithm for the llliac network). We analyze Batcher's bitonic sorting method and show how each network can implement it on an SIMD machine. We discuss how sorting destination tags is equivalent to simulating interconnections.

The MASC (Multiple Associative Computing) model is a generalized associative-style computational model that naturally supports massive data-parallelism and also control-parallelism. A wide range of applications has been developed on this model. Recent research has compared its power to the power of other popular parallel models such as the PRAM and MMB models using simulations. However, the simulation of MMB has identified some important issues regarding the cost of certain basic MASC operations required for associative computing such as broadcasts, reductions, and associative searches. This paper investigates these issues and gives background information and an analysis of timings for these operations, based on implementation techniques and comparison fairness with respect to other models. It aims to provide justification and clarify arguments on the timings for these constant-time or nearly constant-time basic MASC operations.

A different paradigm is needed for real-time command and control (C&C) problems.  Past approaches, using multiprocessors (MP), for real-time computing have had great difficulty in meeting real problem requirements.  We review some reasons why C&C problems that require a solution on a MP architecture may be intractable, and then show an architecture where these reasons for intractability are nonexistent.  We describe a polynomial time solution to the air traffic control (ATC) problem, which is a typical C&C problem. This solution uses a static, non-preemptive table driven schedule using a SIMD architecture called an associative processor (AP). The AP is an ideal processor for set and database operations since its single thread instruction stream can operate on an entire set of data with each instruction.  The AP eliminates multi-thread instructions, which account for much of the MP intractability mentioned above.

A Unified Modeling Language (UML) description of the BSP model of parallel computation is presented. This UML description identifies BSP classes and objects and specifies various object and inter-object relationships, dependencies, and behaviors. This was achieved by describing various views of the BSP model using many of the UML structural and behavioral diagrams. The use to the UML to describe the BSP model has been highly effective for further parallel modeling techniques, comparisons to other parallel models, BSP parallel system software research, and BSP algorithm development.