Architecture of a massively parallel processor

Department of Computer Science
Author(s)
Abstract

The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.
Format
Article
Identifier(s)
10.1145/800053.801922
Publication Date
1980-05
Publication Title
Proceedings of the 7th Annual Symposium on Computer Architecture
Publisher
Association for Computing Machinery
First Page
168
Last Page
173
Keywords
Subject
Rights
http://rightsstatements.org/vocab/InC/1.0/
Community
Department of Computer Science
Permalink https://oaks.kent.edu/kenneth-e-batcher-collection/architecture-massively-parallel-processor
Batcher, K. (1980). Architecture of a massively parallel processor. Proceedings of the 7th Annual Symposium on Computer Architecture. https://doi.org/doi.org/10.1145/800053.801922
Batcher, Kenneth. 1980. “Architecture of a Massively Parallel Processor”. Proceedings of the 7th Annual Symposium on Computer Architecture. https://doi.org/doi.org/10.1145/800053.801922.
Batcher, K. Architecture of a Massively Parallel Processor. Proceedings of the 7th Annual Symposium on Computer Architecture, May 1980, doi:doi.org/10.1145/800053.801922.