Implementing a scalable ASC processor

Department of Computer Science
Author(s)
Abstract

Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.
Format
Article
Identifier(s)
10.1109/IPDPS.2003.1213482
Publication Date
2003
Publication Title
Proceedings of the 17th International Parallel and Distributed Processing Symposium
Publisher
IEEE
Subject
Rights
http://rightsstatements.org/vocab/InC/1.0/
Community
Department of Computer Science
Comments

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Wang, H., & Walker, R. (2003). Implementing a scalable ASC processor (1–). Proceedings of the 17th International Parallel and Distributed Processing Symposium. https://doi.org/10.1109/IPDPS.2003.1213482
Wang, Hong, and Robert Walker. 2003. “Implementing a Scalable ASC Processor”. Proceedings of the 17th International Parallel and Distributed Processing Symposium. https://doi.org/10.1109/IPDPS.2003.1213482.
Wang, Hong, and Robert Walker. Implementing a Scalable ASC Processor. Proceedings of the 17th International Parallel and Distributed Processing Symposium, 2003, https://doi.org/10.1109/IPDPS.2003.1213482.