Collected works of Kenneth E. Batcher, emeritus professor, and works inspired by his research and scholarship.
Browse the Kenneth E. Batcher Collection: Papers from the Parallel and Associative Computing Laboratory Collections
Efficient Implementation of Air Traffic Control Using the ClearSpeed CSX620 System2009Past approaches for air traffic control (ATC) problems use MIMD solutions and have severe problems meeting the requirements of ATC. We propose a new and efficient solution to the ATC problem using SIMD architecture ClearSpeed CSX620. This solution uses synchronous processing of jobs and proposes a new tracking algorithm that can estimate states accurately and a new conflict detection and resolution(CD&R) algorithm that can guarantee the qualities of safety and efficiency. A preliminary prototype of the proposed method has been developed on the ClearSpeed CSX620 and results are presented. |
Elementary Functions in the MPP PE12/15/1978Goodyear technical report GER-16627 (From front matter) This report shows how various elementary functions can be performed in the MPP PE. See the functional description of the MPP PE (GER-16624) for a description of the PE and its operation codes. The functions discussed here are Boolean logic functions, negation, PE address generation, integer addition, integer subtraction and searching. |
Functional description of ASPRO: The high speed associative processor07/16/1984Goodyear Aerospace Corporation technical report GER-16868 |
Implementing a scalable ASC processor2003Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism. |
Implementing associative processing: Rethinking earlier architectural decisions04/2001This paper describes an initial design of an associative processor for implementation using field-programmable logic devices (FPLDs). The processor is based loosely on earlier work on the STARAN computer, but updated to reflect modern design practices. We also draw on a large body of research at Kent State on the ASC and MASC models of associative processing, and take advantage of an existing compiler for the ASC model. The resulting design consists of an associative array of 8-bit RISC Processing Elements (PEs), operating in byte-serial fashion under the control of an Instruction Stream (IS) Control Unit that can execute assembly language code produced by a machine-specific back-end compiler. |
Implementing Associative Search and Responder Resolution04/2002In a paper presented last year at WMPP'01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). That paper presented an overview of the design, and concentrated on the processor's instruction set and its implementation using FPLDs. This paper describes the implementation of the processor's associative operation -- associative searching and responder resolution -- in more detail. |
Importance of SIMD Computation Reconsidered2003In this paper, SIMD and MIMD solutions for the real-time database management problem of air traffic control are compared. A real-time database system is highly constrained in a multiprocessor and access to the common database must be made to a limited number of data elements at a time. This MIMD database access is contrasted with the comparable SIMD common database access, which can be several hundred times greater. This is true because the SIMD can simultaneously access thousands of pertinent records instead of the limited number in the MIMD. A relatively simple example is given of a problem that has a polynomial time solution using a SIMD but for which a polynomial time solution using a MIMD is normally impossible. The fact that SIMD can support a polynomial time solution for the air traffic control problem but this problem is normally considered to be intractable for multiprocessors argues against the common belief that MIMD have greater power than SIMD. SIMD are more efficient and powerful for some critically important application areas. |
Massively parallel processor (MPP): July 1979 phase I final report07/23/1979Goodyear Aerospace Corporation technical report GER-16684 |
MPP: A supersystem for satellite image processing1982In 1971 NASA Goddard Space Flight Center initiated a program to develop high-speed image processing systems. These systems use thousands of processing elements (PE's) operating simultaneously to achieve their speed (massive parallelism). A typical satellite image contains millions of picture elements (pixels) that can generally be processed in parallel. In 1979 a contract was awarded to construct a massively parallel processor (MPP) to be delivered in 1982. The processor has 16,896 PE's arranged in a 128-row by 132-column rectangular array. The PE's are in the array unit (Figure 1). Other major blocks in the massively parallel processor are the array control unit, the staging memory, the program and data management unit, and the interface to a host computer. |