With recent advances in VLSI technology, it is easy to develop chips containing hundreds or thousands of processors - in effect, SIMD processing on a chip. Associative SIMD processing goes further, providing efficient parallel methods for searching tabular data. The techniques described here show that associative processing can also be extended to efficiently process non-tabular structured data (e.g., trees), as we demonstrate by supporting structure codes in our associative ASC processor.

Past approaches for air traffic control (ATC) problems use MIMD solutions and have severe problems meeting the requirements of ATC. We propose a new and efficient solution to the ATC problem using SIMD architecture ClearSpeed CSX620. This solution uses synchronous processing of jobs and proposes a new tracking algorithm that can estimate states accurately and a new conflict detection and resolution(CD&R) algorithm that can guarantee the qualities of safety and efficiency. A preliminary prototype of the proposed method has been developed on the ClearSpeed CSX620 and results are presented.

Goodyear technical report GER-16627

(From front matter)

This report shows how various elementary functions can be performed in the MPP PE. See the functional description of the MPP PE (GER-16624) for a description of the PE and its operation codes.

The functions discussed here are Boolean logic functions, negation, PE address generation, integer addition, integer subtraction and searching.

Goodyear Aerospace Corporation technical report GER-16868

Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.